In a drive control system as may be used in an industrial application requiring the precise control of motor performance, it is known that the transport time delay associated with the thyristor power supply that supplies armature current to the DC motor is the limiting factor which determines how fast the current regulator system can be made. It should be noted that the transport time delay is defined as the time between gating the thyristors and updating the speed controller whether it is a microprocessor or analog type of control system. If a motor armature current regulator is slow, its performance will be erratic, which results in excessive current limit overshoot and can even cause speed regulator instability. It can be appreciated that in an industrial application such as a steel rolling mill where a drive system must control the speed of the rollers for instance, it is essential to have a precise and timely response to speed regulation in order to ensure that the proper gauge and thickness of the steel slab is being maintained. Other industrial applications such as an automated assembly line have similar drive control system considerations as well.
In an analog-based speed control arrangement for a DC motor drive, energy is provided to the armature of the motor by a thyristor power supply. With this configuration, there can be a high armature current rate change when the thyristor power supply goes through zero current in connection with a current reversal. Additionally, it is known that this high armature current rate change can adversely effect the DC motor and can also result in drive speed regulator oscillations. Such conditions can arise in analog speed control arrangement which utilizes proportional integrator squared (PI).sup.2 control characteristics; an example of such an arrangement can be found in U.S. Pat. No. 3,983,464 which issued on Sept. 28, 1976 to the same inventor as the present invention. Another example of a speed control arrangement for a DC motor can be found in U.S. Pat. No. 3,950,684 which issued on Apr. 13, 1976 to same inventor as the present invention.
In a conventional analog speed control arrangement, there is typically a continuous updating of the speed control components until the instant that the thyristors are gated. Although it would seem that the transport time delay under these circumstances would be the time between two successive thyristor gatings, in actuality, this time is typically on the order of 0.4 msec. If such time delay were the time between two successive thyristor gatings, the value for a six pulse, 60 Hz thyristor power supply would be (1/60) (1/6)=2.78 msec. This distinction comes about as a result of the continuous updating between the two successive thyristor gatings; the speed controller sees a transport time delay of 2.78 msec just after gating and a transport time delay of 0.0 msec just prior to gating where the statistical transport time delay used for purposes of controller feedback loop analysis is approximately 0.4 msec.
The transport time delay is more well defined in a microprocessor based digital speed control arrangement; typically in this configuration, the microprocessor would be updated in fixed time intervals of 2.78 msec for a six pulse, 60 Hz system. Since the transport time delay is defined as the time between gating the thyristors and updating the digital speed controller, if the thyristor gate angle is being phased "on", the transport time delay will initially decrease and conversely, if the gate angle is being phased "back", the transport time delay will initially increase. Additionally, since the microprocessor clock is not synchronized to the gating of the thyristor, this condition will further add to the variation of the transport time delay. The resultant effect of such performance characteristics is that the system dynamics become unpredictable; for example, the small step reference response will vary depending on what transport time delay exists when the small step reference is applied to the system.
An example of a microprocessor based digital control arrangement for controlling the firing of a thyristor can be found in U.S. Pat. No. 4,577,269 which issued on Mar. 18, 1986 to A. Abbondanti. In this patent a microprocessor is used to implement sequential thyristor firing at selected delay angles. A numerical master ramp count supplied to the microprocessor by a first timer at the AC fundamental frequency is effective such that individual ramp counts are calculated, these individual ramp counts relating to the individual thyristors to be fired in sequence. The microprocessor calculates the number of units of time needed until a zero count on the individual ramp is reached, the microprocessor performing this function by comparing a delay angle reference count to the individual ramp count. A second timer is also utilized and is preset to an initial count equal to the calculated number of units of time. When the second timer is run to countdown, the next to be fired thyristor is fired. Though effective for its intended purpose of sequentially firing thyristors for a solid state AC-DC converter system, the arrangement of this invention could prove to be quite costly and, because of the two-timer arrangement, cumbersome to implement for the purpose of optimizing the transport time delay associated with the drive control system.